单片CMOS电路所固有的寄生双极晶体管和p-n-p-n通路可能被触发到所不希望的低电阻和高电流状态即产生闭锁现象。为了确保将来的按比例缩小的CMOS电路能安全地工作,因此需要一个精确的闭锁模型以便使设计最佳化。 曾经开发过一个改进型的集总电阻模型,只要能精确地测量器件参数并在闭锁状态反映这些参数,该模型就能精确地预示闭锁特性。该模型包含由一个电阻网络来等效的衬底扩展电阻效应且它在闭锁特性中是一个关键参数。本文还报导了支持这种模型的实验数据。 CMOS电路中的反向设计产大地改善了闭锁保特电流,同时也表征了由电路输入端外电压过冲引起的闭锁动态特性。表明存在一个引起闭锁触发的最小导通时间,并由因高注入效应而增强了扩散系数的横向晶体管的基区滚越时间来决定。 Parasitic bipolar transistors and p-n-p-n paths inherent in a monolithic CMOS circuit can be triggered to undesirably low resistance and high current conditions to create a latch-up. To ensure that future CMOS scaling down circuits can work safely, an accurate latch-up model is needed to optimize the design. An improved lumped-resistor model has been developed that accurately predicts the latching characteristics as long as the device parameters are accurately measured and reflected in the latched state. The model contains a substrate extension resistance effect equivalent to that of a resistor network and it is a key parameter in the blocking characteristics. This article also reports experimental data that supports this model. The reverse design in the CMOS circuit greatly improves the latch-up current and also characterizes the latch-up dynamics due to the external voltage overshoot at the input of the circuit. Indicating that there is a minimum on-time that triggers the latch-up trigger and is determined by the base-roll time of the lateral transistor that increases the diffusion coefficient due to the high injection effect.