论文部分内容阅读
Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.
Digital low-density parity-check (LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue To some extent. However, due to the lack of automation tools and analoguing stop criteria, the analog LDPC decoders suffer from costly handcraft designs and additional decoding delays, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and reduced to decoding delay. Then, a (480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35 -μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3 m W, an d the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.