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4 电路技术为实现ELVIC (初级纵向集成电路),重要的是减少VI (纵向互连)数和VI 的面积,以使集成密度更高.而且制造成品率及器件的可靠性也明显地改善.这一节,研究使内CMOSELVIC 的VI 数最小.图4表示的有3级输出缓冲器电路的两层31级内CMOS 环形振荡器有36个10×10μm~2面积的金-钛纵向互连.应该注意,一个单一的反相器级使用一个纵向互连.就是把同一级的p 沟和n 沟的MOS FET 的漏端用单一的VI 连接起来.这种思想可以扩展到其它的内CMOS 逻辑门.图8证明,使用单一的VI 也可以制造出用于逻辑电路中的2输入NAND 门.同样,多于
4 Circuit Technology In order to realize ELVIC (Primary Longitudinal Integrated Circuit), it is important to reduce the number of VIs (vertical interconnections) and the area of VI so that the integration density is higher, and the manufacturing yield and the reliability of the device are also remarkably improved. In this section, the study minimized the number of VIs within the CMOSELVIC.Figure 4 shows a two-stage, 31-stage, internal CMOS ring oscillator with three output buffer circuits with 36 gold-titanium vertical interconnects of 10x10μm ~ 2 area It should be noted that a single inverter stage uses a vertical interconnect that connects the drain terminals of the same p-channel and n-channel MOS FETs with a single VI, a concept that can be extended to other internal CMOS Logic Gate Figure 8 demonstrates that using a single VI can also create a 2-input NAND gate for logic circuits. Also, more than