论文部分内容阅读
基于集总式电阻-电容树形功耗模型,考虑了非均匀温度分布对互连线电阻的影响,提出了一种新的分布式互连线动态功耗解析模型,解决了集总式模型不能表征非均匀温度变化带来的电阻变化的问题,并计算了一次非理想的激励冲激下整个互连模型消耗的总能量.基于所提出的分布式互连线功耗模型,计算了纳米级互补金属氧化物半导体(CMOS)工艺典型长度互连线的Elmore延时和功耗,发现非均匀温度分布对互连功耗的影响随着互连线长度的增加而增加,单位长度功耗随着CMOS工艺特征尺寸的变化而基本不变.文中所提出的功耗模型可以用来精确估算互连线动态功耗,适用于片上网络构架中大型互连路由结构和时钟网络优化设计.
Based on the lumped resistance-capacitance tree power model, considering the effect of non-uniform temperature distribution on the resistance of interconnects, a new dynamic model of distributed interconnection dynamic power analysis is proposed, which solves the problem of lumped model Can not characterize the resistance variation caused by non-uniform temperature changes, and calculate the total energy consumed by the entire interconnection model under a non-ideal excitation impulse. Based on the proposed distributed interconnect power model, Elmore latency and power dissipation for a typical length interconnection of a CMOS process, it is found that the effect of the non-uniform temperature distribution on interconnect power consumption increases with the length of the interconnect, and the power dissipation per unit length With the change of CMOS process feature size, the power consumption model proposed in this paper can be used to accurately estimate the dynamic power consumption of interconnects and is suitable for large interconnection routing architecture and clock network optimization design in on-chip network architecture.