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为满足中速率高质量语音通信系统的需要 ,采用数字信号处理器内核 (DSP Core)的方法 ,设计了具有国际电信联盟 (ITU )建议 G.72 9A语音编解码器、自适应回声抵消和单路同步功能的专用芯片。根据所用数字信号处理器内核的特点 ,对 G.72 9A算法进行了优化 ,降低了算法复杂度和所需存储空间 ,实现了 G.72 9A全部功能 ,并通过了全部ITU测试序列的检验。回声抵消部分使用归一化最小二乘(NL MS)自适应滤波器实现 ,并设计了近端语音活动性检测和非线性残余回声抑制等功能模块 ,使其性能完全符合 ITU建议 G.16 5各项指标要求。在单路同步模块中 ,使用了并行模二比特排除方法 ,具有同步扑捉快、抗信道误码能力强的优点。专用芯片使用较少的资源 ,在一块芯片上集成了以上全部功能
In order to meet the needs of medium-rate and high-quality voice communication system, the digital signal processor core (DSP Core) method is used to design an ITU-T G.72 9A speech codec with adaptive echo cancellation and single Road synchronization function of the special chip. According to the characteristics of digital signal processor core used, the G.72 9A algorithm is optimized, which reduces the algorithm complexity and required storage space, realizes all the functions of G.72 9A and passes the examination of all ITU test sequences. The echo cancellation part is implemented by a normalized least squares (NL MS) adaptive filter, and functional modules such as near-end voice activity detection and non-linear residual echo suppression are designed to fully comply with the performance of ITU recommendation G.16 5 The requirements of the indicators. In the single-channel synchronization module, the parallel mode two-bit elimination method is used, which has the advantages of quick synchronization acquisition and fast anti-channel error tolerance. Dedicated chips use less resources, integrated in a single chip all the above features