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在超大规模集成电路的自动化设计中 ,用电路同构验证方法解决设计结果的验证问题是非常有用的。提出了一种电路同构验证的方法 ,利用高效的集簇算法建立电路的层次化结构 ,从而极大地减少同路同构验证过程中的 CPU运行时间和所需要的内存。实验结果表明 ,与 HCNC方法相比 ,该方法的验证时间要少很多 ,尤其在对称性比较高的大电路的验证上 ,不存在内存溢出的问题 ,而且和理论分析一致。
In the automated design of VLSI, it is very useful to solve the problem of design verification by using circuit isomorphism verification. A method of circuit isomorphism verification is presented. The hierarchical structure of the circuit is established by using an efficient clustering algorithm, so as to greatly reduce the CPU running time and the required memory in the isomorphism verification process. Experimental results show that compared with the HCNC method, the verification time of this method is much less, especially in the verification of large circuits with high symmetry, there is no memory overflow problem, and it is consistent with the theoretical analysis.