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为了降低芯片成本,通过使用低压器件串联的方式构造静电防护触发电路,使芯片在没有使用高压I/O器件的情况下实现了高压电源域的ESD防护。由于该触发电路未使用电容器件,因此有效地降低了ESD触发电路所占用的芯片面积,并且该电路为静态电压触发,其开启时间可远长于一般电容电阻耦合的触发电路。通过在HSPICE中使用类ESD(ESD-like)的方波脉冲,可以看出该电路在发生ESD时能有效地触发ESD器件,而在芯片正常工作时不易因外界干扰而产生误触发。
In order to reduce the cost of the chip, the electrostatic protection trigger circuit is constructed by using the low-voltage devices in series so that the chip can achieve the ESD protection of the high-voltage power domain without using high-voltage I / O devices. Since the trigger circuit does not use a capacitor device, the chip area occupied by the ESD trigger circuit is effectively reduced, and the circuit is triggered by a static voltage, and the turn-on time of the circuit can be much longer than that of a general-purpose capacitive resistor-coupled trigger circuit. By using an ESD-like square wave pulse in HSPICE, it can be seen that this circuit effectively triggers the ESD device in the event of ESD, and is not susceptible to false triggering due to outside interference during normal operation of the chip.