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该文提出了一种以两位加法器模块构成的静态进位跳跃加法器,通过对加法器尺寸的优化方块分配、方块之间的互补进位产生以及方块内部的多级超前进位逻辑3种方法获得快速静态进位跳跃加法器。当第一个方块的进位信号产生以后,其它每个方块从进位输入到进位输出仅需一个复合门的延时。已用PSPICE仿真工具对其进行了功能验证和仿真。通过门级延时分析和仿真结果比较,所提出的进位跳跃加法器的速度具有超前进位加法器的速度优势。
This paper presents a static adder hopping adder with two adder modules. Through the optimization of the adder size, the complementary carry generation between the blocks and the multi-level advance carry logic within the block, three methods Get fast static carry skip jump adder. After the carry signal of the first block is generated, only one delay of the composite gate is required for each of the other blocks from carry input to carry output. PSPICE simulation tools have been used to verify the function and simulation. By comparing the gate-level delay analysis with the simulation results, the speed of the carry-skip adder proposed has the advantage of advancing the speed of the carry adder.