介绍了一个采用折叠内插结构的 CMOS模数转换器 ,适合于嵌入式应用 .该电路与标准的数字工艺完全兼容 ,经过改进的无需电阻就能实现的折叠模块有助于减小芯片面积 .在输入级 ,失调平均技术降低了输入电容 ,而分布式采样保持电路的运用则提高了信号与噪声的失真比 .该 2 0 0 MHz采样频率 8位折叠内插结构的 CMOS模数转换器在 3.3V电源电压下 ,总功耗为 177m W,用 0 .18μm3.3V标准数字工艺实现 A CMOS analog-to-digital converter with folded interpolation architecture is introduced for embedded applications, which is fully compatible with standard digital processes, and improved folding blocks that do not require resistors can help reduce the chip area. In the input stage, the offset averaging technique reduces the input capacitance, while the use of distributed sample-and-hold circuits increases the signal-to-noise distortion ratio. The 200 MHz sampling frequency 8-bit folded interpolation CMOS analog-to- 3.3V power supply voltage, the total power consumption of 177m W, with 0.18μm3.3V standard digital technology