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A novel triple RESURF(T-resurf) SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_(sp) is reduced from 16.5 to 13.8 mΩ·cm~2 in comparison with the double RESURF(D-resurf) SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV~2/R_(on).It reduces R_(sp) by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.
A novel triple RESURF (T-resurf) SOI LDMOS structure is proposed. This structure has a P-type buried layer. Firstly, the depletion layer can extend on both sides of the P-buried layer, serving as a triple RESURF and leading to a high drift doping and a low on-resistance. Secondarily, at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side, which results in uniform bulk electric field distributions and an enhanced BV. The proposed structure is used in SOI devices for the first time. The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6 μm-thick SOI layer over a 2 μm- thick buried oxide layer, and its R_ (sp) is reduced from 16.5 to 13.8 mΩ · cm ~ 2 in comparison with the double RESURF (D-resurf) SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV ~ 2 / R_ (on) .It reduces R_ (sp) by 25% in 400 VS OI LDMOS and by 38% in 550 V SOI LDMOS compared with the D-resurf structure.