本文提出利用标准单元或优化阵列外围单元(I/O)灵活性,设计模拟单元积木块。模拟积木块以库的形式存在,和数字单元一样具有自动设计能力,且这一设计可使数模部分在芯片上相对独立,有助于单元的长效性、灵活性,以及各自的布线和工艺调整。利用标准单元或优化阵列法均可实现数模兼容设计,兼容电路设计周期、成本与全数字电路相近。 This paper proposes the design of a simulation unit building block using either standard cell or optimized array peripheral (I / O) flexibility. Analog blocks exist in the form of a library that has the same automatic design capabilities as digital cells, and this design allows the digital-to-analog sections to be relatively independent on the chip, contributing to the long-term flexibility of the cells and their individual wiring and Process adjustment. The use of standard cells or optimized array method can achieve digital-analog compatible design, compatible circuit design cycle, the cost of digital circuits and similar.