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本文根据MPEG-2视频编码的特点,设计了仅由一个1-DCT核完成的2-DCT/IDCT结构,该结构的转换矩阵通过SRAM实现,具备双端口的输入输出,数据吞吐率较高,能够有效节省芯片面积.1-DCT核由7个乘法器组成,乘法器可以根据计算速度的快慢灵活设计.为了解决双端口无冲突的存储访问,提出了一个数据排列方案.由于乘法器的乘数之一为常数,我们设计了一种常数修改方案能够有效的降低成法器的硬件开销.该2-DCT/IDCT结构通过了FPGA验证,具有较强的工程实用价值.
According to the characteristics of MPEG-2 video coding, this paper designs a 2-DCT / IDCT structure which is only composed of one 1-DCT core. The conversion matrix of this structure is realized by SRAM, with dual-port input and output, Can effectively save the chip area.1-DCT core consists of seven multipliers, the multiplier can be based on the speed of computing flexibility in the design. In order to solve the two-port conflict-free memory access, a data arrangement scheme is proposed. One of the constants is constant, and we designed a constant modification scheme which can effectively reduce the hardware cost of the synthesizer. The 2-DCT / IDCT structure has passed FPGA verification and has strong engineering practical value.