论文部分内容阅读
在复杂的超大规模高速集成电路设计中,时钟树的综合与优化是芯片后端设计优化时序过程中至关重要的一环,其中时钟树的设计是最关键的部分。以SMIC 0.13μm工艺双频双系统兼容接收机数字基带导航芯片为例,根据时钟树时序要求和时钟树延迟模型,基于Synopsys的Astro工具,对芯片进行自动时钟树分析和指定时钟树结构分析,设计和优化了时钟树结构。结果表明,利用此方法得到的时钟树结构能取得更优的结果。
In the design of complex ultra-large-scale high-speed integrated circuits, clock tree synthesis and optimization of the chip back-end design optimization timing is a crucial part of the process, including the design of the clock tree is the most crucial part. Taking SMIC 0.13μm process dual-band dual-system compatible receiver digital baseband navigation chip as an example, according to the clock tree timing requirements and clock tree delay model, based on Synopsys’ Astro tool, automatic clock tree analysis and specified clock tree structure analysis, Design and optimize the clock tree structure. The results show that the clock tree structure obtained by this method can achieve better results.