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采用注入势垒单相埋沟结构和两层多晶硅一层铝工艺技术,研制出512位高速CCD延迟线,获得了大于10 MHz的工作频率和大于50 dB的动态范围。器件电极设计为准1相两层多晶硅交迭栅结构,信道设计为埋沟结构。输入结构采用双输入栅表面势平衡注入技术,输出结构采用浮置扩散源跟随放大器技术。提出了改善转移效率、暗电流、时钟频率和动态范围的有效方法。测试结果表明,器件性能参数达到设计要求。
A 512-bit high-speed CCD delay line was developed by injecting a single-phase buried-barrier structure with a barrier layer and a two-layer polysilicon aluminum process technology. The operating frequency is greater than 10 MHz and the dynamic range is greater than 50 dB. The device electrode is designed as a quasi-1-phase polysilicon overlapped gate structure, and the channel is designed as a buried-trench structure. The input structure adopts double-input gate potential balance injection technology, and the output structure adopts floating diffusion source to follow the amplifier technology. An effective method to improve the transfer efficiency, dark current, clock frequency and dynamic range is proposed. The test results show that the device performance parameters meet the design requirements.