【摘 要】
:
Systolic implementation of multiplication over GF(2m) is usually very efficient in area-time complexity,but its latency is usually very large.Thus,two low laten
【机 构】
:
School of Information Science and Engineering, Central South University, Changsha 410083, China
【基金项目】
:
国家自然科学基金;the Natural Science Foundation of Hunan Province,China
论文部分内容阅读
Systolic implementation of multiplication over GF(2m) is usually very efficient in area-time complexity,but its latency is usually very large.Thus,two low latency systolic multipliers over GF(2m) based on general irreducible polynomials and irreducible pentanomials are presented.First,a signal flow graph (SFG) is used to represent the algorithm for multiplication over GF(2m).Then,the two low latency systolic structures for multiplications over GF(2m) based on general irreducible polynomials and pentanomials are presented from the SFG by suitable cut-set retiming,respectively.Analysis indicates that the proposed two low latency designs involve at least one-third less area-delay product when compared with the existing designs.To the authors’ knowledge,the time-complexity of the structures is the lowest found in literature for systolic GF(2m) multipliers based on general irreducible polynomials and pentanomials.The proposed low latency designs are regular and modular,and therefore they are suitable for many time critical applications.
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