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A 35–130 MHz/300–360 MHz phase-locked loop frequency synthesizer for Δ–Σ analog-to-digital converter(ADC) in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode(300–360MHz) or in low-power mode(35–130 MHz) to satisfy the ADC’s requirements. To switch between these two modes,a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the frequency synthesizer achieves a phase-noise of –132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of –112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.
A 35-130 MHz / 300-360 MHz phase-locked loop frequency synthesizer for Δ-Σ analog-to-digital converter (ADC) in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode (300- 360MHz) or in low-power mode (35-130MHz) to satisfy the ADC’s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the frequency synthesizer achieves a phase-noise of -132 dBc / Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of -112 dBc / Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.