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为改善现有鉴频鉴相器(PFD)中存在的问题,从理论分析的角度对现有的PFD进行了研究,并对其进行了基于电路结构的分类与比较.提出并设计了一种应用于高速低抖动电荷泵锁相环的高鲁棒性新型鉴频鉴相器.该PFD由2个上升沿触发的动态D触发器、2个上升沿检测和延时模块及2个或门组成.由于融合了2种复位机制,能避免UP与DN信号同时为高电平,因此,电荷泵的电流失配将不会恶化PLL的性能.而且,该PFD的鉴相特性中几乎没有鉴相死区.设计及仿真是基于1·8V电源电压的TSMC0·18μm CMOS工艺.由理论推导和电路仿真可知,该PFD具有高工作频率(≈ 1GHz)、高可靠性、宽鉴相范围([±2π])、零死区(<0·1ps)、低抖动、低功耗(≈100μW)、低复杂度等特性.
In order to improve the existing problems of PFD, the existing PFD is studied theoretically and the classification and comparison based on the circuit structure are carried out. A High-performance, low-jitter charge-pump phase-locked loop phase-locked loop with high robustness of the new phase-frequency detector.The PFD consists of two rising edge triggered dynamic D flip-flop, two rising edge detection and delay module and two OR gates The combination of the two reset mechanisms prevents the UP and DN signals from being high at the same time, so that the current mismatch of the charge pump will not degrade the performance of the PLL, and there is little to no discrimination between the phase characteristics of the PFD Phase-to-dead zone.The design and simulation are based on TSMC0 · 18μm CMOS technology with 1.8V supply voltage.The theoretical derivation and circuit simulation show that the PFD has high operating frequency (≈1GHz), high reliability, wide detection range [ ± 2π]), zero dead band (<0.1ps), low jitter, low power consumption (≈100μW) and low complexity.