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[会议论文] 作者:Jih-Ren Goh,Yen-Long Lee,Soon-Jyh Chang,
来源:2015 International Symposium on VLSI Design, Automation and 年份:2015
This paper presents a dual-edge sampling clock-embedded signaling CES DLL based CDR.By combining the proposed dual edge sampling and half-UI embedded clock codi...
[会议论文] 作者:Tien-Feng Hsu,Chun-Po Huang,I-Jen Chao,Soon-Jyh Chang,
来源:2015 International Symposium on VLSI Design, Automation and 年份:2015
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