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数模混合片上系统(SoC)正逐步成为片上系统的主导,而其中模拟芯核的测试问题是研究的难点之一。利用自保持模拟测试接口(SHATI)可以实现模拟芯核对外接口虚数字化,对其进行并行测试。该文对自保持模拟测试接口进行了面积优化,以减少片上DFT(design for test)面积开销,并利用Hspice仿真实验验证了面积改进的可行性。同时,针对并行测试的测试激励调度问题,该文给出了测试时序设计的优化算法,并通过实际示例验证了算法的可行性。
Digital-analog hybrid system-on-chip (SoC) is gradually becoming the dominant system-on-chip, and the simulation of the core test problem is one of the difficulties. Using self-sustaining analog test interface (SHATI) can simulate the core virtual interface digital virtualization, its parallel test. This paper optimizes the self-maintaining analog test interface to reduce the design for test (DFT) area overhead and verifies the feasibility of area improvement by Hspice simulation. At the same time, aiming at the problem of test stimulus scheduling in parallel test, an optimization algorithm of test sequence design is given. The feasibility of the algorithm is verified through practical examples.