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由于寄存器文件严重影响可重构密码处理器的性能和面积,为了实现高性能和低面积消耗的密码处理器,提出了一种高效的分布式跨域寄存器结构.通过分析不同分组密码的算法特点,设计了统一的多端口访问结构——分布式跨域寄存器文件.针对全局寄存器文件和局部寄存器文件不同的算法需求,在TSMC40 nm CM OS工艺下,采用不同设计参数分别完成电路实现并与类似结构做比较.实验结果显示,所提出的分布式跨域寄存器结构能够有效地提升单位面积的性能,其中单位时间分组密码性能提升了17.79%,单位面积时间分组密码性能提升了117%.
Because register files seriously affect the performance and area of reconfigurable cryptographic processors, an efficient distributed cross-domain register structure is proposed in order to achieve high performance and low area consumption cryptographic processors. By analyzing the characteristics of algorithms of different block ciphers , Designed a unified multi-port access structure - distributed cross-domain register file.According to the different algorithm requirements of global register file and local register file, using different design parameters in TSMC40 nm CM OS process to achieve the circuit and similar The experimental results show that the proposed distributed cross-domain register structure can effectively improve the performance per unit area, among which the performance per unit time block cipher improves by 17.79% and the performance per unit area time block cipher improves by 117%.