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近年发展的双采样技术（double sampling）[1]是提高sigma-delta调制器信噪比的一种有效的方法，而电容的失配是影响其信噪比的重要因素。分析表明，双采样技术在三阶系统中的应用，电容失配引起前馈信号混叠，由此产生的噪声对系统信噪比的影响不可忽略。本文提出了一种结合ILA DAC[2]和前端完全浮动电容结构的电路形式，将这种结构应用在第二级调制器的积分器上，使双采样电容失配产生的噪声远小于量化噪声，从而满足了三阶调制器的性能要求。
The double sampling [1] developed in recent years is an effective way to improve the signal-to-noise ratio of the sigma-delta modulator. The mismatch of capacitance is an important factor affecting the signal-to-noise ratio of the sigma-delta modulator. The analysis shows that the double sampling technique is applied in the third-order system, the mismatch of capacitance causes the aliasing of the feedforward signal, and the influence of the noise produced on the signal to noise ratio of the system can not be neglected. This paper presents a circuit combining ILA DAC [2] with front-end fully floating capacitor structure. When this kind of structure is applied to the integrator of the second-stage modulator, the noise caused by the double sampling capacitor mismatch is far less than the quantization noise , Thus meeting the performance requirements of the third-order modulator.