据日本《电子材料》2003年第8期报道,日本东芝公司在65nm CMOS工艺线成功地开发了世界最低功耗的晶体管。该晶体管采用氮化铪(HfSiON)作为高介电率栅氧化膜,控制了Si衬底的界面反应,确保了界面稳定性;此外采用等离子体氮化技术用HfSiON材料形成了高介电率膜。与Si氧化膜相比,栅漏电流降低至其1/1000的水平。HfSiON材料由于具有组成均一性的优 According to Japan’s “Electronic Materials” 2003 the eighth period reported that Toshiba Japan 65nm CMOS process line successfully developed the world’s lowest power transistors. The transistor adopts HfSiON as a high-dielectric gate oxide film to control the interfacial reaction of the Si substrate to ensure the interfacial stability. In addition, the HfSiON material is used to form the high dielectric constant film . Compared with the Si oxide film, the gate leakage current is reduced to 1/1000 of its level. HfSiON materials have the advantage of composition uniformity