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主要研究具有不同传输速率的多路同步数据和异步数据的无线传输,具体地,将具有2Mb/s和4Mb/s的2路同步数据和8路9.6kb/s的异步数据合并起来进行无线传输。重点研究传输的硬件接口设计和组帧方式。采用ALTERA公司的FPGA芯片,以FIFO为核心,将写请求端和数据写入端用于控制各路数据的接收,将接收到的数据缓存在FIFO中;并将读请求端和数据读出端用于控制各路数据的组帧。该设计用VHDL语言编程,在QuartusⅡ环境下完成了功能仿真。仿真结果表明,该系统能够完成多路数据的合并传输。
It mainly studies the wireless transmission of multi-channel synchronous data and asynchronous data with different transmission rates. Specifically, 2-channel synchronous data with 2Mb / s and 4Mb / s and 8-channel 9.6kb / s asynchronous data are combined for wireless transmission . Focus on the transmission of the hardware interface design and framing mode. Using ALTERA company’s FPGA chip, the FIFO as the core, the write request and data write end for controlling the data received, the received data is buffered in the FIFO; and the read request and data read-out Used to control the framing of each data. The design using VHDL language programming, completed in the Quartus Ⅱ environment functional simulation. Simulation results show that the system can accomplish the combined transmission of multiple data.