随着集成电路速度的提高,大多数脉冲和函数发生器的上升时间和下降时间(典型值为5ns)就不宜于测量20ns以下的时间间隔。采用模拟比较器或高级CMOS逻辑门电路可以产生更快的数字沿,从而可消除这一限制。这些比较器或逻辑门电路的上升和下降时间足够快,但其信号电平仅有地电位和V_(cc)两种。设计人员也已将高速数字电路使用的亚微米工艺应用于模拟开关,所以这些模拟开关的 As the speed of integrated circuits increases, the rise and fall times (typically 5 ns) for most impulse and function generators are not appropriate for measuring time intervals below 20 ns. Eliminating this limitation is the use of analog comparators or advanced CMOS logic gates to produce faster digital edges. The rise or fall times of these comparators or logic gates are fast enough, but their signal levels are only ground and V cc. Designers have also applied sub-micron technology used in high-speed digital circuits to analog switches, so these analog switches