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精简指令系统计算机例如MIPS2000VLSIRISC处理机由于流水线的每一级完全由有用的计算作业所占用,从而获得最高的计算性能,为了做到这点需要在计算算法上删除多余的不需要的步骤。先进的优化编译器技术能够排除多余的步骤,例如冗长的地址计算,代码发生器软件一个周期接着一个周期地控制流水线操作。这样可能做到处理机的指令系统主要由单周期指令组成。处理机简化的结果,能够制造出快速的在计算性能上无可比拟的超大规模集成电路器件。事实上,性能受限制不是由于修理机的速度,而是对指令和数据提供足够带宽的存贮系。Cache存贮器和主存缓冲器是提供这个带宽的关键。静态随机访问存贮器SRAM。先进先出缓冲器FIFO和按内容可选址的存贮器CAM技术是限制因素。
Reduced Instruction System Computers such as the MIPS2000VLSIRISC processor get the highest computational performance because each stage of the pipeline is completely occupied by useful computational jobs, and in doing so requires removing unnecessary unwanted steps from the computational algorithm. Advanced, optimized compiler techniques eliminate redundant steps such as lengthy address calculations and code generator software to control pipeline operations cycle by cycle. This may be done processor instruction system consists of single-cycle instructions. The processor simplifies the result and can produce very fast VLSI devices that are unmatched in computational performance. In fact, performance is not limited by the speed of the repairer, but rather by a storage system that provides sufficient bandwidth for instructions and data. Cache memory and main memory buffer is the key to provide this bandwidth. Static random access memory SRAM. First-In-First-Out buffers FIFO and content-selectable memory CAM technology are the limiting factors.