论文部分内容阅读
研究了VelociTI结构浮点数字信号处理器寄存器堆的流水线读写原理并提出了一种设计方法。该方法对单操作数双精度浮点指令采用2个32位数据通路用1个流水线周期读取源操作数,双操作数双精度浮点指令采用锁定译码单元,利用若干流水线周期读取源操作数。采用写控制向量的方法实现了流水线多个周期执行写操作。该方法正确实现了基于IEEE754标准的双精度浮点数据在寄存器堆与功能单元之间的32位数据通路上的传输,仿真结果验证了其正确性。
This paper studies the principle of pipeline read and write of VelociTI structure floating point digital signal processor register file and presents a design method. This method uses two 32-bit datapaths to read the source operand in one pipeline cycle for single-operand double-precision floating-point instructions, the lock-decode unit for double-operand double-precision floating-point instructions, and uses several pipeline cycle read sources Operands. Using write control vector method to achieve the pipeline multiple cycles to perform the write operation. The method realizes the transmission of double-precision floating-point data based on IEEE754 standard on the 32-bit data path between the register file and the functional unit. The simulation results verify the correctness.