本文叙述了一台交换复合装置的设计中所采用的种种故障检测、例行程序考验、和诊断技术。与别的电子交换系统(ESS)处理机不同,该处理机完全是自校验的。 由于充分发挥微程序设计和实时余量(excess real time),只需增添少量设备就可以并行检测出处理机中大多数的故障。如果从开始方案设计时就注意对硬件、软件、和维修能力等进行全面考虑和调整,就能把这样的自校验性能运用到机器的设计上。 硬件校验对处理机的故障检测起着重要作用。这些技术包括奇偶校验、译码器的N中取1校验、双规判别、总计时器、以及自校验的时钟机构。采用微程序挖制的错误检测技术包括寄存器——寄存器传送的全符合校验、保证指令按正确的次序执行的顺序校验、和存贮器的先写后读校验。 处理机的多数故障由上述的一种技术并行检测。不能并行检测的那些故障(通过用计算机模拟辨别)和维修逻辑用频繁的程序考验来校验。通过处于指令级或微指令级的处理机以及用本机维修中心执行程序考验。当呼叫存贮器(CS)中有故障时,例行程序考验还参与决定出现故障的设备。对简化诊断过程方面作了深入的研究。处理机的组装和所提供的测试通路为许多故障的诊断分辨提供了方便。 处理机实现所有这些特性的详细的门电路设计已经完成。为了验证自校验的 This article describes a variety of fault detection, routine testing, and diagnostic techniques used in the design of a switching compound. Unlike other electronic switching system (ESS) processors, the processor is completely self-verifying. With the best of micro-program design and excess real time, most of the faults in the processor can be detected in parallel with just a few additional devices. If you start with the design plan to pay attention to the hardware, software, and maintenance capabilities to fully consider and adjust, you can put this self-check performance into the design of the machine. Hardware verification plays an important role in processor fault detection. These techniques include parity, decoder N check 1, dual rules, total timers, and self-checking clock mechanisms. Error detection techniques using microprogramming include register-register-all-coincidence verification, sequence verification to ensure that instructions execute in the correct order, and memory write-after-read-verification. Most of the processor failures are detected in parallel by one of the techniques described above. Those failures that can not be detected in parallel (by using computer simulations) and maintenance logic are verified with frequent program tests. Pass the processor at instruction level or micro-instruction level, and perform the program test with the local service center. When there is a fault in the call store (CS), the routine test also participates in the decision of the failed device. To simplify the diagnosis process made in-depth research. The assembly of the processor and the test paths provided facilitate the diagnostic resolution of many faults. Detailed gate design for the processor to achieve all of these features has been completed. In order to verify self-checking