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提出了一种数字锁相环(DPLL) ,它的相频检测器采用全新的设计方法和自校准技术,具有工作频率范围宽,抖动低,快速锁定的优点.锁相环在1·8V外加电源电压时,工作在60 ~600 MHz的频率范围内.采用分数分频技术,加速锁定过程并具有较小的输出频率间隔,利用Σ-Δ调制改善相位噪声性能.设计在SMIC 0·18μm,1·8V,1P6 M标准CMOS工艺上实现,峰-峰相位抖动小于输出信号周期的0·8 %,锁相环的锁定时间小于参考频率预分频后信号周期的150倍.
A digital phase-locked loop (DPLL) is proposed, whose phase-frequency detector adopts a new design method and self-calibration technique and has the advantages of wide operating frequency range, low jitter and fast locking. The power supply voltage, the work in the 60 ~ 600 MHz frequency range. Fractional frequency divider technology to accelerate the locking process and has a smaller output frequency interval, the use of Σ-Δ modulation to improve the phase noise performance.Designed at SMIC 0.18μm, 1.8V, 1P6M standard CMOS technology. The peak-to-peak phase jitter is less than 0.8% of the output signal period, and the PLL lock time is less than 150 times the signal period after the reference frequency prescaler.