As the feature size of the CMOS integrated circuit continues to shrink,process variations have become a key factor affecting the interconnect performance.Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method,we propose a linear statistical RCL interconnect delay model,taking into account process variations by successive application of the linear approximation method.Based on a variety of nano-CMOS process parameters,HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%.The proposed model is simple,of high precision,and can be used in the analysis and design of nanometer integrated circuit interconnect systems. As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. proposed proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.