用常规工艺技术已研制成功一种存储电容器几乎占用了全部单元面积的DRAM单元。因此我们发现,即使用300A的介质材料,该存储电容也能改进以前报导过的256k DRAM存储单元的结果。在不使用多晶硅化物,双层金属工艺或多行译码器的条件下,提高性能是可能的。 该单元的布局如图1所示,用辅加掩蔽工艺形成隐埋扩散位线,这种辅加的掩蔽工艺能在淀积多晶硅1和正常源/漏注入之前,注入位线和氧化。多晶硅1字线在其与有源区重叠而又没有位线注入的地方形成存取晶体管。用这种方法,多晶硅1字线能跨越隐埋位线而不形成晶体管。多晶硅1还为外围电路形成晶体管。利用多晶硅2和多晶硅3形成存储电容器 A conventional DRAM cell has been developed that uses a memory capacitor that occupies almost the entire area of ​​the cell. So we found that even with 300A of dielectric material, this storage capacitor can also improve the previously reported 256k DRAM cell results. It is possible to improve performance without the use of polycide, double-layer metallization or multi-row decoders. The layout of this cell is shown in Figure 1. The buried diffusion bit line is formed using a complementary masking process that can inject bit lines and oxidize prior to deposition of polysilicon 1 and normal source / drain implantations. The polysilicon 1 word line forms an access transistor where it overlaps the active area without bit line injection. In this way, the polysilicon 1 word line can cross the buried bit line without forming a transistor. The polysilicon 1 also forms a transistor for the peripheral circuit. The polysilicon 2 and the polysilicon 3 form a storage capacitor