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提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.
A new quasi-static single-phase energy recovery logic is proposed, which is different from the previous energy recovery logic and realizes the single-phase power clock without any additional auxiliary control clock, not only reduces the energy consumption but also greatly simplifies The design of the clock tree also allows the logic to reach the speed of logic for two-phase energy recovery. An 8-bit log-ahead carry adder is designed and implemented using traditional static CMOS logic, clocked CMOS adiabatic logic Of single-phase energy recovery logic) and quasi-static single-phase energy recovery logic implementation.Using 128 randomly generated input test vector simulation results show that: the input frequency of 10MHz, quasi-static energy recovery logic energy consumption is only the traditional static CMOS 45% of logic; when the input frequency is greater than 2MHz, you can get lower than the clock-controlled CMOS adiabatic logic energy consumption.