提出了一种改进的分布式算法和一种具有流水线结构的加法树乘法器,设计了一种在FPGA上实现的FIR数字滤波器。介绍了改进的DA算法,对采用FPGA实现直接型结构移位相加乘法器FIR滤波器和改进DA算法的高速FIR滤波器的性能进行了比较。用VHDL在Quartus II平台上进行了仿真,给出了实现高效滤波功能的设计结果及不同算法的资源占用比较。 An improved distributed algorithm and an additive tree multiplier with pipeline structure are proposed. An FIR digital filter implemented on FPGA is designed. The improved DA algorithm is introduced, and the performance of high-speed FIR filter using FPGA with direct structure shift addition and multiplication FIR and improved DA is compared. Using VHDL simulation on the Quartus II platform, the design results of efficient filtering and the resource consumption comparison of different algorithms are given.