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In this letter,we design and analyze 0.1-1.5 GHz multi-octave quadruple-stacked CMOS power amplifier (PA) in 0.18μm CMOS technology.By using two-stage quadruple-stacked topology and feedback technology,the proposed PA realizes an ultra-wideband CMOS PA in a small chip area.Wideband impedance matching is achieved with smaller chip dimension.The effects of feedback resistors on the RF performance are also discussed for this stacked-FET PA.The PA shows measured input ret loss (＜-10.8 dB) and output ret loss (＜-9.6 dB) in the entire bandwidth.A saturated output power of 22 dBm with maximum 20％ power added efficiency (PAE) is also measured with the drain voltage at 5 V.The chip size is 0.44 mm2 including all pads.