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介绍了面阵CCD485的内部结构、工作模式,并给出了其基本驱动电路设计。然后通过对面CCD485驱动时序图的分析,分析了全帧型大面阵CCD的正常工作、快速擦除、图像窗口输出和像元合并的驱动时序,提出了一种基于时序细分和有限状态机的通用型全帧型面阵CCD驱动时序发生器设计方法。该方法通过对CCD驱动时序进行分组,将每一组时序的波形划分为若干个基本输出状态,这样CCD各个工作阶段所需的驱动时序都可以由各基本状态组合出来,使用摩尔型有限状态机来描述,将时序驱动器进行了模块化设计。给出了各个模块的具体设计,使时序发生器的设计过程更加简单,最后采用Xilinx公司的Virtex-ⅡPro系列FPGA-XC2VP20、ISE软件平台,设计了CCD驱动时序发生器,并进行了波形仿真分析。输出信号完全满足485芯片的驱动时序要求,证明了该设计方法的有效性。
The internal structure and operating mode of CCD CCD 485 are introduced, and the design of its basic driving circuit is also given. Then, through the analysis of the timing diagram of the CCD485 driver, the normal operation, fast erasing, output of the image window and driving timing of the binning of the full-frame large area CCD are analyzed. A timing subdivision and finite state machine Universal Full-Frame Array CCD Driving Timing Generator Design Method. The method divides the timing of CCD driving into several elementary waveforms and divides the waveforms of each timing into several basic output states. In this way, the driving timings required by each working stage of CCD can be combined by each basic state. By using Moore finite state machine To describe, the timing driver has been a modular design. The design of each module is given to make the design process of the timing generator simpler. Finally, the CCD driver timing generator is designed by Virtex-ⅡPro series FPGA-XC2VP20 and ISE software from Xilinx, and the waveform simulation analysis . The output signal completely meets the driving timing requirements of the 485 chip, which proves the effectiveness of the design method.