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在布局、网络列表和可综合的寄存器传送级格式中,内核已经成为芯片设计方法的一个完整部分。芯片是高度集成化的,元件密度很高,设计人员又要抢时间,尽早地把产品推向市场。因此,如何重复利用内核及其它形式的设计便成为很重要的问题。但是,设计人员在内核的设计、复杂芯片的内核互连以及组装内核测试程序方面却面临着许多难题。这次座谈会把电子设计自动化供应商、内核和固件设计公司的代表召集在一起。来讨论这些关键性的问题。
The core has become an integral part of the chip design approach in layout, network list, and synthesizable register transfer level formats. The chip is highly integrated, high component density, designers have to grab the time, the product as soon as possible to the market. Therefore, how to reuse the kernel and other forms of design has become a very important issue. However, designers face many challenges with the design of the kernel, the inter-core interconnect of complex chips, and the assembly of kernel test programs. This forum brought together representatives of electronic design automation vendors, cores and firmware design houses. To discuss these key issues.