集成电路中金属连线的逆流电迁移(EM)的双峰失效现象在45 nm双大马士革低k材料铜布线工艺中变得尤为突出,介绍了由于空洞存在于连接电路导致电迁移的早期失效,总结出两个早期失效的主要原理:分别是空洞形成在通孔以及浅槽与通孔的斜面,这是由于淀积扩散阻挡层和铜工艺在上述两个地方存在弱点,越薄的扩散阻挡层厚度对EM越不利。因为偏薄的扩散阻挡层不利于阻挡铜扩散,尤其在通孔的侧壁和边角斜面,这样在测试电迁移的高温大电流下,铜在通孔侧壁和边角斜面处易扩散而形成空洞,最终导致芯片失效。实验表明可以通过优化双大马士革结构通孔以及浅槽与通孔的斜面的长宽比(AR)减少消除这些弱点。介质层(ILD)的厚度,浅槽的深度以及通孔的关键尺寸可以作为调节AR的主要方法。 The bimodal failure of the countercurrent electromigration (EM) of metal interconnects in integrated circuits has become particularly prominent in the 45 nm dual damascene low-k copper interconnect process. The early failure of electromigration due to the presence of voids in the connecting circuits was introduced, Two main principles of early failure are summarized: voids are formed in vias and bevels of shallow trenches and vias, respectively, due to the presence of weaknesses in both the deposited diffusion barrier and the copper process, the thinner diffusion barrier The layer thickness is less favorable to EM. Because the thin diffusion barrier is not conducive to blocking the copper diffusion, especially in the side walls of the through-hole and the bevel, so in the test electromigration high temperature and high current, the copper in the through-hole sidewall and the bevel edge of the easy to spread The formation of voids, eventually leading to chip failure. Experiments have shown that these weaknesses can be eliminated by optimizing the aspect ratio (AR) reduction of dual damascene via and shallow bevel to via. The thickness of the dielectric layer (ILD), the depth of the shallow trenches, and the critical dimensions of the vias can be the primary method of adjusting the AR.