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随着深亚微米ＩＣ和时钟速度超过５０ＭＨｚ的印制板不断普及，设计师必须注意研究元器件之间的连接。直到最近以前，大多数ＩＣ或ＰＣＢ设计师都不太在意互连线延迟。但现在已有一些人开始寻找适当的ＥＤＡ工具以预估互连线延迟对整个设计的影响。可喜的是，今天的ＰＣ和工作?
As deep sub-micron ICs and boards with clock speeds above 50 MHz continue to proliferate, designers must pay attention to studying the connectivity between components. Until recently, most ICs or PCB designers did not care much about interconnect delay. But now some people have begun to find the right EDA tools to predict the impact of interconnect delay on the entire design. The good news is that today’s PC and work?