Development of graphene field effect transistors (GFETs) faces a serious challenge of graphene interface to the dielectric material.A single layer of intrinsic graphene has an average sheet resistance of the order of 1-5 kΩ/□.The intrinsic nature of graphene leads to higher contact resistance yielding into the outstanding properties of the material.We design a graphene matrix with minimized sheet resistance of 0.185 Ω/□ with Ag contacts.The developed matrices on silicon substrates provide a variety of transistor design options for subsequent fabrication.The graphene layer is developed over 400 nm nickel in such a way as to analyze hypersensitive electrical properties of the interface for exfoliation.This work identifies potential of the design in the applicability of few-layer GFETs with less process steps with the help of analyzing the effect of metal contact and post-process annealing on its electrical fabrication.