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提出了一种应用于高速串行链路中的基于二阶预加重和阻抗校正技术的6 Gbit/s低功耗低抖动电压模(VM)发送器。在综合分析阻抗、供电电流和输出驱动器预加重等因素影响的基础上,采用了多种技术来提高发送器的信号完整性,主要包括:设计了一种阻抗校正电路(ICU)以保证50Ω的输出阻抗并抑制信号反射,提出了一种自偏置稳压器用来稳定电源电压,同时设计了一种信号边沿驱动器用以加速信号的转换时间。最终,整个发送器在65 nm CMOS工艺平台进行设计。后仿真结果表明,发送器工作在6 Gbit/s时,远端输出眼图高度大于800 m V,均方根抖动小于2.70 ps。发送器的功耗为16.1 m A,占用面积仅为370μm×230μm。
A 6 Gbit / s low power, low jitter voltage mode (VM) transmitter based on second-order pre-emphasis and impedance correction techniques is proposed for use in high-speed serial links. Based on the analysis of impedance, supply current and output driver pre-emphasis and other factors, a variety of techniques are used to improve the signal integrity of the transmitter, including: Designing an impedance correction circuit (ICU) to ensure 50Ω Output impedance and inhibit signal reflection, a self-bias regulator is proposed to stabilize the supply voltage and a signal edge driver is designed to accelerate the signal transition time. In the end, the entire transmitter was designed on a 65 nm CMOS process platform. Post-simulation results show that when the transmitter is operating at 6 Gbit / s, the far-end output eye pattern height is greater than 800 mV and the root-mean-square jitter is less than 2.70 ps. The power consumption of the transmitter is 16.1 m A, occupying an area of only 370 μm × 230 μm.