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设计了一种1.8～3.3 V的自偏置LDO电路,无需外加基准电路,且具有良好的负载调整率和工艺兼容性。该电路采用无需双极型晶体管的基准电路,并且在负载电压和负载电流之间采用电流倍增电路进行隔离,减小了负载电流瞬变造成低压差线性稳压器(LDO)输出电压的变化,提高了LDO的瞬态精度。在关键器件部分采用匹配结构,以减小工艺误差对电路性能造成的影响。基于0.18μm SOI CMOS工艺,用Hspice软件进行电路仿真,用Cadence软件进行版图验证。仿真结果表明,MOS基准电路产生的基准电压温漂为5.6×10-5,LDO的最大负载电流为100 mA,负载电流瞬变的响应时间小于1.5μs,负载调整率为0.3%,整体电路的静态电流为88μA,芯片尺寸为650μm×1 200μm。
A 1.8 ~ 3.3 V self-biased LDO circuit is designed without external reference circuit and has good load regulation and process compatibility. The circuit uses a bipolar transistor-free reference circuit and uses a current multiplying circuit to isolate the load voltage from the load current. This reduces the load voltage transients that can cause changes in the LDO output voltage, Improves LDO transient accuracy. In the key part of the device using matching structure to reduce the impact of process error on the circuit performance. Based on the 0.18μm SOI CMOS process, Hspice software was used to simulate the circuit and verify the layout with Cadence software. The simulation results show that the reference voltage drift generated by MOS reference circuit is 5.6 × 10-5, the maximum load current of LDO is 100 mA, the response time of load current transients is less than 1.5μs and the load regulation rate is 0.3% The quiescent current is 88μA and the chip size is 650μm × 1 200μm.