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由于寄存器传输级 (RTL)行为描述可以精确地确定数字系统的操作 ,所以寄存器传输级综合成为当前EDA行业的主流设计方法 .实现从寄存器传输级行为描述到门级结构描述转换的 RTL 综合 ,是组合逻辑 /时序逻辑综合理论在 HDL(硬件描述语言 )上的具体应用 .设计寄存器传输级综合工具的基础是格式判别 ,即将行为描述中的组合逻辑与时序逻辑区分开来 ,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合 .在分析和总结寄存器传输级行为描述规律以及逻辑综合局限性的基础上 ,论述格式判别的必要性、可行性、有效性 ,提出一种易于实现的格式判别方法 .该方法利用赋值语句为核心的中间数据格式以及逻辑综合所能接受的内部格式 (多维体 ) ,将复杂的寄存器传输级行为描述分解为各个赋值语句组 ,根据赋值语句组中的各条赋值语句的条件判断此赋值语句组是组合逻辑还是时序逻辑 ,并生成不同层次、功能相对独立的 RT单元以便利用对应的组合逻辑综合或时序逻辑综合处理此 RT单元 ,从而在实现 RTL 综合的过程中使组合逻辑综合和时序逻辑综合得到最大限度的重用 .最后文中给出一些测试实例和结果分析 .通过测试实例和结果分析表明该文提出的方法不但有效地区分了组合逻辑和时序逻辑 ,而且由于通过对组合?
Since register-transfer-level (RTL) behavioral descriptions accurately determine the operation of a digital system, register-transfer-level synthesis has become the mainstream design approach of the current EDA industry. Implementing RTL synthesis from register-transfer-level behavior descriptions to gate-level structure description transformations is The specific application of combinatorial logic / sequential logic synthesis theory in HDL (Hardware Description Language) The basis for the design register transfer-level synthesis tool is format discrimination, that is, the combinatorial logic in behavioral description is separated from temporal logic, Sequential logic synthesis, respectively, to complete the register transfer level synthesis.Based on the analysis and summary of the register transfer level behavioral description of the law and the logic of the integrated limitations, discusses the necessity of format discrimination, feasibility and effectiveness of an easy to implement This method uses the intermediate data format with the assignment statement as its core and the internal format (multidimensionality) accepted by the logic synthesis to decompose the complex register-transfer-level behavior description into each assignment statement group, and according to the assignment statement group Of the assignment statement of the article Determine whether the assignment statement group is combinational logic or sequential logic and generate RT units with different levels and relatively independent functions so as to synthesize the RT unit by using the corresponding combined logic synthesis or the sequential logic so that in the process of implementing the RTL synthesis, Synthesis and sequential logic synthesis are reused to the maximum extent.Finally, some test cases and result analysis are given.According to the test case and the result analysis, it is shown that the proposed method not only effectively separates combinatorial logic and sequential logic, ?