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本文研究了轻掺杂漏（ＬＤＤ）工艺对器件特性的影响。优化了轻掺杂区离子注入的剂量和能量．优化的ＳｉＯ２侧墙ＬＤＤ工艺有效地抑制了短沟道效应．研制成功了沟道长度为０．５μｍ的ＣＭＯＳ２７级环振电路，门延迟为１７０ｎｓ．
This article studies the effects of lightly doped drain (LDD) processes on device characteristics. The dose and energy of ion implantation at lightly doped regions are optimized. The optimized SiO2 sidewall LDD process effectively suppresses short channel effects. The successful development of the channel length of 0.5μm CMOS27 ring oscillator circuit, the gate delay of 170ns.