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在硅集成电路进一步缩小尺寸的过程中,将会遇到一些困难;其中的一项是栅氧化层的厚度,从目前情况来看出现了问题得以解决的苗头。解决的方案是采用结晶的氧化物作栅极介
One of the difficulties in further shrinking the size of silicon ICs is the thickness of the gate oxide. The current situation shows that problems have been solved. The solution is to use crystalline oxide gate dielectric