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JK触发器具有R。ST和D触发器的特征,并被广泛地应用于数字系统里。但是,JK触发器的电路结构比较复杂,而且其功率耗损比其它型式的触发器都高。在大规模集成中,JK触发器的电路复杂性和大功耗就限制了其实现。一般地说来,一个JK触发器是把RS触发器的输出经过反馈路径连到输入端而构成的,如图1中所示。然而,当J和K两者输入端都为高时,高时钟状态将引起空转。一些共知的解决办法,能用于克服这种空转问题。列举其中两个如下。
JK trigger has R. ST and D flip-flop features, and is widely used in digital systems. However, JK flip-flop circuit structure is more complicated, and its power consumption is higher than other types of flip-flop. In large-scale integration, JK flip-flop circuit complexity and high power consumption limits its implementation. In general, a JK flip-flop is formed by connecting the output of an RS flip-flop to the input via a feedback path, as shown in FIG. However, when both J and K inputs are high, the high clock state will cause idle. Some commonly known solutions can be used to overcome this idling problem. Cite two of them as follows.