论文部分内容阅读
采用后台校正技术,通过对级间余量放大器传输函数建模来估计误差,以提高流水线型ADC(analog to digital converter,ADC)的性能。为了在校正精度、硬件消耗、功率消耗和算法收敛速度之间做一个合理的权衡,需要在建模时选用一个合理的插值算法。以一个12位,采样频率40兆的流水线型ADC为原型,分别采用分段线性插值、三次多项式插值对第一级余量放大器传输函数建模,用硬件描述语言Verilog对系统进行描述,结合模拟电路部分进行混合仿真验证,运用综合工具对两种算法对应的Verilog程序进行综合估计。仿真结果表明:两种算法中,分段线性插值法硬件消耗和功耗更低,而多项式插值法校正精度更高,算法收敛更快。
Using background correction technique, the error is estimated by modeling the transfer function of interstage headroom amplifier to improve the performance of analog to digital converter (ADC). In order to make a reasonable trade-off between accuracy of calibration, hardware consumption, power consumption and convergence rate of the algorithm, a reasonable interpolation algorithm needs to be adopted in modeling. A 12-bit, 40-MHz pipelined ADC was used as a prototype, and the transfer function of the first stage residual amplifier was modeled by piecewise linear interpolation and cubic polynomial interpolation respectively. The system was described by hardware description language Verilog, The circuit part carries on the mixed simulation verification, uses the synthesis tool to carry on the comprehensive estimate to the Verilog procedure corresponding to the two kinds of algorithms. The simulation results show that the piecewise linear interpolation method has lower hardware consumption and lower power consumption, while the polynomial interpolation method has higher accuracy and faster convergence.