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针对传统仲裁器物理不可克隆函数(PUF)在FPGA上实现后唯一性很差,而且资源消耗代价大的问题,在分析FPGA Slice的结构基础上,设计了一种新型结构的仲裁器PUF电路,该电路大幅度地提高了唯一性,大大减少了FPGA的资源消耗,使得仲裁器PUF可应用于FPGA.基于此提出了一种对传统仲裁器PUF结构改进的方案,利用Slice之间的对称性来提升PUF的唯一性,并充分利用Slice内部的组合逻辑资源以降低资源消耗.实验测量了片间海明距离和片内海明距离,评估了64bit的仲裁器PUF电路的唯一性和稳定性,结果表明:改进后的仲裁器PUF非常适合在FPGA上实现,能够降低62.5%的资源消耗,并且唯一性比较接近理想值.
Aiming at the problem that the traditional unclonable function (PUF) of the arbiter is not unique in the FPGA, and the resource consumption is expensive, a new architecture PUF circuit is designed based on the analysis of the structure of the FPGA slice. This circuit greatly improves the uniqueness and greatly reduces the resource consumption of the FPGA, so that the arbiter PUF can be applied to the FPGA. Based on this, a scheme for improving the structure of the traditional arbiter PUF is proposed. By utilizing the symmetry between slices To improve the uniqueness of PUF and to make full use of the combinational logic resources in Slice to reduce the resource consumption.This experiment measured the distance between Hamming and the Hamming distance on chip and evaluated the uniqueness and stability of the 64 bit arbiter PUF circuit, The results show that the improved arbiter PUF is very suitable for implementation on FPGA, which can reduce the resource consumption by 62.5% and the uniqueness is close to the ideal value.