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优化了芯片版图结构,采用常规工艺制作了SiC MESFET大栅宽芯片。优化了管壳内芯片装配形式,采用电容及电感匹配网络提高了器件阻抗,提高了器件增益。设计并优化了3 dB电桥输入及输出匹配电路,保证了器件最大功率输出及工作稳定性。最终采用管壳内四胞合成及外电路3 dB电桥合成的方法,突破了S波段SiC MESFET多胞大功率合成技术,实现了器件脉冲输出功率达百瓦量级。四胞26 mm大栅宽芯片合成封装后的器件,在测试频率2 GHz、工作电压VDS为56 V、脉宽为50μs、占空比为1.5%工作时,脉冲输出功率为300.3 W,增益为9.2 dB,漏极效率为36.6%,功率附加效率为32.2%。
Optimized chip layout structure, the use of conventional technology made SiC MESFET large gate wide chip. Optimized the assembly form of the chip in the package, using capacitor and inductor matching network to improve the impedance of the device and improve the gain of the device. The 3 dB bridge input and output matching circuit is designed and optimized to ensure the maximum power output and stability of the device. Finally, the method of synthesizing the quadruplets in the package and the 3 dB bridge circuit of the external circuit is adopted, which breaks through the multi-cell high-power synthesis technology of the S-band SiC MESFET and achieves the pulse output power of the device up to the magnitude of one hundred watts. The quadruple 26-mm wide gate-wide chip package was fabricated at a test frequency of 2 GHz with an operating voltage VDS of 56 V, a pulse width of 50 μs and a duty cycle of 1.5% with a pulse output of 300.3 W at a gain of 9.2 dB, the drain efficiency of 36.6%, power added efficiency of 32.2%.