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设计了一款与CSMC 0.5μm CMOS工艺兼容的频率为500 MHz的辐照加固整数型锁相环电路,研究了总剂量辐照以及单粒子事件对锁相环电路主要模块及整个系统性能的影响。此外,通过修正BSIM3V3模型的参数以及施加脉冲电流源来模拟总剂量辐照效应和单粒子事件,对锁相环整体电路进行了电路模拟仿真以及版图寄生参数提取后仿真。模拟结果表明,辐照总剂量为1Mrad(Si)时锁相环电路仍能正常工作,产生270.58~451.64 MHz的时钟输出,峰峰值抖动小于100 ps,锁定时间小于4μs;同时在对单粒子事件敏感的数字电路的主要节点处施加脉冲电流源后,锁相环电路均能在短时间内产生稳定的输出。
The design of a radiation-locked integer PLL with frequency of 500 MHz that is compatible with CSMC 0.5μm CMOS process and the effects of total dose irradiation and single-event on the main modules and overall system performance of the PLL are studied . In addition, by modifying the parameters of BSIM3V3 model and applying pulse current source to simulate the total dose radiation effect and single-event, the circuit simulation of phase-locked loop integrated circuit and the post-simulation extraction of layout parasitic parameters were carried out. The simulation results show that the PLL can still work normally when the total radiation dose is 1 Mrad (Si), resulting in a clock output of 270.58 ~ 451.64 MHz with a peak-to-peak jitter of less than 100 ps and a locking time of less than 4 μs. After applying the pulse current source at the main node of the sensitive digital circuit, the phase-locked loop circuit can produce the stable output in a short time.