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在考虑了电导率调制效应的情况下对深亚微米静电放电(electrostatic discharge,ESD)保护器件的衬底电阻流控电压源模型进行优化,并根据轻掺杂体衬底和重掺杂外延型衬底的不同物理机制提出了可根据版图尺寸调整的精简衬底电阻宏模型,所建模型准确地预估了不同衬底结构上源极扩散到衬底接触扩散间距变化对触发电压Vt1的影响.栅接地n型金属氧化物半导体器件的击穿特性结果表明,所提出的衬底电阻模型与实验结果符合良好,且仿真时间仅为器件仿真软件的7%,为ESD保护器件版图优化设计提供了方法支持.
The substrate resistance controlled voltage source model of the deep submicron electrostatic discharge (ESD) protection device is optimized considering the conductivity modulation effect. Based on the lightly doped substrate and the heavily doped epitaxial The different physical mechanisms of the substrate propose a simplified substrate resistance macro-model that can be adjusted according to the layout size. The model accurately predicts the influence on the trigger voltage Vt1 of the variation of the contact diffusion distance between the source diffusion and the substrate on different substrate structures . The breakdown characteristics of the gate-grounded n-type metal-oxide-semiconductor devices show that the proposed substrate resistance model is in good agreement with the experimental results and the simulation time is only 7% of the device simulation software, providing the layout optimization for ESD protection devices Method support.