本文提出了一种基于时域交织技术的级联∑Δ调制器新结构 ,保留了原有时域交织结构的速度优势 ,克服了它的缺点 ,且电路简单 ,具有实用价值 .对 1- 1级联、4路并行的情况进行模拟的结果表明 :新结构比普通 2阶∑Δ调制器 ,相同时钟速率下转换精度提高 3bit,同样精度要求下转换带宽扩大一倍 ,对各路增益失配等电路非理想因素不敏感 . In this paper, a new structure of cascaded ΣΔ modulator based on time-domain interleaving is proposed, which preserves the speed advantage of the original time-domain interleaving structure, overcomes its shortcomings and has simple circuit and practical value. The results show that the new structure improves the conversion accuracy by 3 bits at the same clock rate compared with the common 2-order ΣΔ modulator, and the doubling of the conversion bandwidth under the same precision requires that the gain of each channel is mismatched Circuit non-ideal factor is not sensitive.